Chapter 8 - External Interrupts, Resets, Operating Modes, and the COP

This chapter describes the 68HC11F1's external interrupts, computer operating properly (COP) feature, clock monitor, low power modes, operating modes, and the 4xOut signal.

Two external interrupts, /IRQ (active-low interrupt request) and /XIRQ (active-low nonmaskable interrupt request) allow external hardware to interrupt the 68HC11F1 (HC11 p.2-17). The / prefix to each of these names indicates that the signals are active-low. Pull-up resistors on the QED Board hold these signals high during normal operation, and an interrupt is recognized when either signal is pulled low by an external source. The /IRQ input is maskable and is not serviced unless the I bit in the condition code register is clear. If the CPU is servicing an interrupt when the /IRQ line goes low, the external interrupt will not be recognized until the interrupt being serviced has been handled. Unlike all the other maskable interrupts, /IRQ does not have a local interrupt mask.

/XIRQ is nonmaskable. After a one-time enabling (clearing) of its X control bit in the CCR, an /XIRQ request will be immediately serviced. For this reason it can be used to warn of critical situations such as impending power failure.

The /IRQ and /XIRQ pins are accessed and controlled via the Digital I/O and Control bus (for pin locations see Appendix A). They operate as active-low inputs to the processor. An external device can drive either of these lines LOW to signal an interrupt. Alternatively, several open-collector devices can be wired together on the same line, so that any one of them can interrupt the processor by pulling the request line low. This is called "wired-or" operation. In either case, the external device must pull the line low long enough to be detected by the CPU.

Note that the PORTA input capture lines described in Chapter 4 can also be configured to interrupt the processor when an external event occurs.

In its default state after each reset or restart /IRQ pin is configured as an edge-triggered input. In this mode, the 68HC11 latches the falling edge, causing an interrupt to be recognized. This frees peripheral devices from having to hold the /IRQ line low until the CPU senses the interrupt, and prevents multiple servicing of a single external event.

The disadvantage of this configuration is that multiple edge-triggered interrupts cannot be reliably detected when used with wired-OR interrupt sources. If you are using multiple wire-or /IRQ inputs, you can specify level-sensitive interrupt recognition by clearing a bit named IRQE (IRQ edge-sensitive) in the OPTION register (HC11 p.5-24). IRQE is a "protected bit" in OPTION that must be written within the first 64 E cycles after a reset. The QED-Forth word INSTALL.REGISTER.INITS (described in the glossary) may be used to specify a value that is automatically stored into OPTION upon each reset.

The /XIRQ external interrupt supports only level-sensitive operation, and is a nonmaskable interrupt. Most interrupts, including /IRQ, are globally disabled ("masked") if the I bit in the condition code register (CCR) is set. /XIRQ is not affected by the state of the I bit. Rather, it is controlled by the X bit in the CCR. Whenever the 68HC11 is reset, the X bit is set in the CCR, thus disabling the /XIRQ external interrupt. The QED-Forth startup routine does not modify the X bit. To use the /XIRQ interrupt, install an appropriate interrupt handler using the ATTACH command, and then enable the /XIRQ interrupt after each reset by clearing the X bit. A short routine that clears the X bit is presented below.

After being enabled, only an in-process /XIRQ service routine or a reset can prevent an /XIRQ interrupt request from being recognized. The /XIRQ interrupt is commonly used to detect power loss as described below.

To use the /IRQ external interrupt, define an interrupt handler and install it using the pre-defined identifier IRQ.ID and the interrupt ATTACH utility:

CFA.FOR <name OF your /IRQ handler> IRQ.ID ATTACH

If interrupts have not yet been enabled globally, execute:

ENABLE.INTERRUPTS

Whenever /IRQ is pulled low, your interrupt handler will be executed. Note that there is no local interrupt mask for the /IRQ interrupt, so your interrupt handler routine need not clear an interrupt request flag.

Similarly, to use /XIRQ, install an interrupt handler using ATTACH by executing

CFA.FOR <name OF your /XIRQ handler> XIRQ.ID ATTACH

Next enable the interrupt by clearing the X bit in the CCR. This can be done by defining and executing the following word:

CODE XIRQ.ENABLE \ define an assembly routine to enable /XIRQ
TPA \ get the CCR contents into accumulator A
BF IMM ANDA \ clear the X bit in bit position 6
TAP \ put result in CCR, clearing X bit to enable /XIRQ
RTS \ return
END.CODE
XIRQ.ENABLE \ execute the word to enable /XIRQ

Now that /XIRQ is enabled, your external interrupt handler will be called whenever the /XIRQ line on the I/O and Control Bus is pulled low. A 68HC11 reset will again set the X bit.

The QED Board's early power-down output signal named /Power.Fail (see Chapter 13) may be connected to the /XIRQ input to warn the processor of an impending power failure. The processor then has a short period of time in which necessary cleanup and data saving operations can be performed before the processor shuts down.

The /Power.Fail signal is an active-low output generated by the power monitoring circuitry on the QED Board. It is asserted (it goes low) when the +5 Volt digital supply (denoted as +5V in the Appendix A connector diagrams) falls to within 0.15 Volts of the voltage at which the /RESET signal is asserted. Assuming a current drain of 100 mA, the time it takes the voltage to drop 0.15 Volts equals

cleanup.time = 1.5 microseconds per microfarad of filter capacitance

A relatively small filter capacitance of 22 µF is installed across the +5V digital supply, so if no additional capacitance is added to the board only 22 * 1.5 = 33 microseconds are available between the power fail warning and the shutdown of the processor. With an interrupt latency of 17 usec (see Chapter 3), only 16 usec is available to the /XIRQ interrupt service routine to perform cleanup operations. To increase the available time, simply connect a capacitor from the +5V supply to digital ground (labeled DGND). +5V and DGND are available at the Power connector, Address/Data bus connector, and the Digital I/O connector.

For example, using the 1.5 microseconds per microfarad relationship, a 470 µF capacitor would allow the /XIRQ interrupt approximately

cleanup.time = [ 1.5 us/µF ] * [ 470 µF ] = 700 microseconds

to "clean up" and save any required data before the processor is shut down by the /RESET signal.

In addition to installing the filter capacitor, you should connect the /Power.fail output (pin 21 on the Digital I/O connector) to the adjacent /XIRQ input (pin 19 on the Digital I/O connector). The following code illustrates the installation of the power fail detection software:

XIRQ.ENABLE   \ your autostart routine should execute this
              \ so that /XIRQ interrupts are enabled
 
: CLEAN.UP.BEFORE.POWER.FAILS ( -- )
    %%...%% perform NEEDED clean-UP functions HERE %%**...%%**
    BEGIN \ enter an infinite loop; wait for power to fail
    AGAIN
;
 
CFA.FOR CLEAN.UP.BEFORE.POWER.FAILS XIRQ.ID ATTACH
              \ install the interrupt handler

Notice that the /XIRQ service routine finishes with an endless loop; it simply waits for power to go down. If we allowed the interrupt service routine to terminate, it would be immediately called again because the /Power.fail signal would still be active -- only this time there would be less time to perform the required clean up!

If your clean-up routine has to perform a lot of functions, consider using a large filter capacitance and/or assembly coding the /XIRQ service routine. Storage of values in EEPROM is not recommended as part of a power-fail clean-up routine, as 20 msec are required to modify each EEPROM byte; instead, consider saving key transient parameters in battery-backed RAM.

Three types of interrupts initiate a hardware reset of the 68HC11:

• Power-on or activation of the reset button
• Computer-Operating-Properly (COP) timeout
• Clock monitor failure

These are the highest priority interrupts, and are nonmaskable. Serviced immediately, they initialize the hardware registers and then execute a specified interrupt service routine. QED-Forth sets the interrupt vectors of these interrupts so that they execute the standard startup sequence. The service routines for all but the main reset interrupt may be changed by the programmer with the ATTACH utility.

The main reset interrupt of the 68HC11 processor is activated upon power-up or when the active-low /RESET signal is pulled low. The processor does not distinguish between a power-on reset and a reset caused by a low level on the /RESET input pin; both result in the same hardware initialization and software restart sequence.

The /RESET line is normally held high by a pull-up resistor. You can pull the /RESET line low by toggling the reset switch (DIP switch #6 on the QED Board). You can also connect a momentary contact switch between /RESET and ground; the /RESET signal is available on both the Address/Data connector and the Digital I/O connector. Moreover, any peripheral device can reset the processor by driving the /RESET signal low for at least 2 microseconds using an open-collector output.

Both the active-low /RESET signal is controlled by the power monitor circuitry. On power-up, the monitor asserts the reset signal until the positive supply has stabilized above 4.5 Volts. Chapter 13 ("Powering the QED Board") describes the functions of the power monitor circuit in detail.

The 68HC11 resets itself when a failure condition is detected by either the computer-operating-properly (COP) or the clock monitor circuit. When either of these failure conditions occur, the processor drives the /RESET line low for less than 4 machine cycles to reset itself and any peripherals that are connected to the /RESET line. The processor then determines which failure (COP or clock monitor) caused the reset, and branches to the associated service routine. QED-Forth initializes the interrupt vectors for the COP and clock monitor to perform the standard restart sequence, and the programmer may change the vectors if desired (see the "Special Reset-Type Interrupts" section in the "Interrupts and Register Initializations" chapter of the QED Software Manual). The operation of the COP and clock monitor are described in the following sections.

In many embedded control applications, it is important that processor crashes be detected quickly so that the system can rapidly be returned to a proper operating condition. The Computer Operating Properly subsystem, also known as a "watchdog timer" or "COP", provides this capability. It gives the programmer a way to force a processor reset if an application program crashes or gets lost. When enabled, the COP resets the processor if the application program fails to periodically update a specified register within a predetermined time-out period. The COP time-out period is programmable to any of four values between 16 milliseconds and 1 second at an 8 MHz crystal frequency; time-out periods range from 8 msec to 0.5 seconds with a 16 MHz crystal.

To use the COP, design and debug an application program that, in addition to performing all of its normal tasks, periodically writes a 2-byte pattern to the COP reset (COPRST) register as described below. The specified pattern must be written before the COP "times out". Then install the application as an autostart routine using the QED-Forth word AUTOSTART, and enable the COP.

If the application program ever allows the time-out period to be exceeded without writing the specified pattern, the COP resets the processor. Presumably the pattern will not be properly written if the processor crashes for any reason, so the COP provides a way of automatically resetting the processor to recover from crashes. Then, because the application program has been installed as an autostart routine, the application is automatically restarted when the COP forces a reset.

Before enabling the COP, make sure that a debugged application program that properly updates the COPRST register has been installed as an AUTOSTART or PRIORITY.AUTOSTART routine. If the startup program is improperly designed so that it is unable to service the COP on time, the COP will reset the machine, thereby invoking the startup program again, and leading to an infinite series of COP resets.

If you find yourself in this situation and you have burned the defective PRIORITY.AUTOSTART routine into a PROM, remove the PROM. If the PRIORITY.AUTOSTART routine is in battery-backed RAM, un-write-protect the RAM. To return the QED Board to its "pristine" state, invoke the special cleanup mode by turning DIP switch #5 ON and resetting the machine. Then return DIP switch #5 to its normal OFF position and reset the processor again to resume normal operation with the COP disabled and any autostart routine removed. Consult the "Interrupts and Register Initializations" chapter in the Software Manual for a description of the special cleanup mode.

The COP feature should prove trouble-free as long as the application program is:

1. fully debugged
2. capable of updating the COPRST in a timely fashion
3. installed as an autostart routine.

Three bits are used to configure and enable/disable the COP. They are named CR0, CR1, and NOCOP. CR0 and CR1 are located in the OPTION register. These bits determine the amount of time which can elapse between updates of the COPRST register by the application program. If the time-out period is exceeded, the COP forces a reset. The four available time-out periods are:

The CR1 and CR0 bits in the OPTION register may be modified only during the first 64 cycles after a reset. The QED-Forth word INSTALL.REGISTER.INITS makes it easy to specify a value that will be automatically stored into the OPTION register after every reset; consult its glossary entry for details, or see the coded example presented below.

The third control bit is called NOCOP and is located in the CONFIG register. The QED-Board is shipped with this bit set so that the COP is disabled. To enable the COP, clear this bit; the example code presented below demonstrates how to do it. The CONFIG register's contents are non-volatile, and so are maintained even after the processor has been powered down.

Servicing the COP is accomplished by writing 55H and AAH to the COPRST register. Although the order of the writes is important, the number of intermediate instructions between them is inconsequential. The two writes must be performed before the time-out period has elapsed. Once AAH has been stored, the COP will need to be serviced again before the next time-out period has elapsed.

The following fast assembly routine updates the COPRST register:

HEX
803A    CONSTANT    COPRST    \ define the COP reset register as a 16-bit address
 
CODE COP.SERVICE
\ Updates the COPRST register.
\ Execution time is 8 usec with an 8 MHz crystal, or 4 usec at 16 MHz
    55AA     IMM    LDD        \ load ACCD with service bytes, 3 cycles
    COPRST EXT    STAA        \ store $55 to COPRST, 4 cycles
    COPRST EXT    STAB        \ store $AA to COPRST, 4 cycles
    RTS                \ return from subroutine, 5 cycles
END.CODE            \ total = 16 cycles = 8 usec @ 8 MHz crystal

Now select a time-out period within which you can guarantee timely updating of the COPRST register, and code a properly working autostart word that periodically calls the COP.SERVICE routine to avoid a COP time-out.

You are now ready to configure and enable the COP. To set the time-out period, the configuration bits CR1 and CR0 in the OPTION register must be set using INSTALL.REGISTER.INITS. To enable the COP, the NOCOP bit in the CONFIG register must be cleared and, as mentioned above, this requires a special procedure. Briefly, the CONFIG register's contents are so important that they cannot be modified unless a special bit called PTCON (protect config) in the BPROT (block protection) register is cleared. To clear the protection bit, INSTALL.REGISTER.INITS must be used. Once this protection bit is cleared, the CONFIG register may be modified using the (EEC!) command; this is because the register is implemented as a non-volatile EEPROM byte. Once enabled, the COP will be active on all subsequent power-up restarts until the NOCOP bit in the CONFIG register is explicitly set.

After the COP is enabled, the next reset activates it. You must ensure that a proper AUTOSTART or PRIORITY.AUTOSTART routine has been installed before the COP becomes active. The following 6 steps show how to set up and activate the COP.

1. Define some useful register and time-out constants, and calculate an appropriate value for the CR0 and CR1 bits in the OPTION register to set up the desired time-out period. This can be accomplished using the following words:

   HEX
   \ define time-out constants assuming an 8 MHz crystal frequency:
   0    CONSTANT    16.384MS
   1    CONSTANT    65.536MS
   2    CONSTANT    262.14MS
   3    CONSTANT    1.049SEC
    
   \ Now define all needed register names.
    
       803F  REGISTER:    CONFIG    \ CONFIG contains bit that enables the COP
       8039  REGISTER:    OPTION    \ OPTION contains CR0 and CR1 time-out bits
       8035  REGISTER:    BPROT    \ BPROT register holds CONFIG protection bit
    
       \ TMSK2 and BAUD contents are needed by INSTALL.REGISTER.INITS
       8024  REGISTER:    TMSK2    \ define name for TMSK2 register
       802B  REGISTER:    BAUD    \ define name for BAUD register
    
    
   \ define a word to calculate the desired contents of the OPTION register
    
   : OPTION.CONTENTS ( time.out.constant -- option.register.contents )
       OPTION C@ FC AND    \ clear CR1 and CR0 bits
       OR                \ set CR1 and CR0 as specified
   ;

   For example, to calculate an appropriate OPTION register value for implementing a 1.049 second time-out period, execute the following:

   1.049SEC OPTION.CONTENTS

2. Use INSTALL.REGISTER.INITS to install the proper values for the OPTION and BPROT registers. We have just calculated the desired contents of the OPTION register. Bit 4 of the BPROT register is the PTCON (protect CONFIG) bit; it must be cleared so that we can write to the CONFIG register to enable the COP. Both OPTION and BPROT must be initialized during the first 64 machine cycles after each reset, and the QED-Forth word INSTALL.REGISTER.INITS can accomplish this. It stores the desired values for the 4 special registers OPTION, TMSK2 (lowest 2 bits only), BPROT, and BAUD in EEPROM, and automatically installs the specified values in the registers after each reset. The following command sequence installs the desired contents of the registers to establish a 1.049 second time-out period for the COP (assuming an 8 MHz crystal frequency), and allows writes to the CONFIG register:

   1.049SEC OPTION.CONTENTS    \ put OPTION contents on data stack
   TMSK2  C@     \ specify current values of PR0 & PR1
   BPROT  C@ 0F AND    \ preserve bits 0-3, clear PTCON bit
   BAUD    C@    \ specify current baud rate
   INSTALL.REGISTER.INITS    \ install register initialization values

   Push the reset button to put the new register values into effect.

3. Install your application program (a QED-Forth word) as an AUTOSTART routine in EEPROM or as a PRIORITY.AUTOSTART routine in page 4 memory (see the "Autostarting" section of the "Program Development Techniques" chapter in the QED Software Manual). The application program must periodically execute COP.SERVICE to update the COPRST register before the time-out period has elapsed. Execute:

   CFA.FOR <name OF your APPLICATION program> AUTOSTART<code> OR
   <code forth>CFA.FOR <name OF your APPLICATION program> PRIORITY.AUTOSTART

   Your autostart word will now be executed after every power-on, reset, or abort. This ensures the COP will always be properly serviced.

4. Enable the COP by clearing the NOCOP bit of the CONFIG register. This is accomplished by executing:

   CONFIG C@ FB AND CONFIG DROP (EEC!)

   which clears bit 2 (NOCOP) while preserving the other bits in the CONFIG register. Note that (EEC!) is used because the CONFIG register is implemented as an EEPROM byte in the hardware register area.

5. Before resetting the machine to activate the COP, it is advisable to again write-protect the CONFIG register. This is accomplished by repeating the INSTALL.REGISTER.INITS as described in step 2 with the exception that the PTCON (protect CONFIG) bit in the BPROT register is set instead of cleared:

   OPTION C@ \ keep current value of OPTION
   TMSK2 C@ \ keep current values of PR0 & PR1 in TMSK2
   BPROT C@ 10 OR \ set PTCON bit in BPROT
   BAUD C@ \ keep current value of BAUD
   INSTALL.REGISTER.INITS

6. Now reset your machine. The COP will be enabled and your autostart routine will be executed automatically.

Although the COP subsystem requires special care during installation and implementation, it provides an ability to recover from crashes that is necessary for many applications. Another feature that helps to ensure proper operation of the processor is the clock monitor.

The clock monitor provides a second level of security by monitoring the main system clock and resetting the processor if the clock signal disappears or oscillates too slowly. The clock monitor does not initiate a reset as long as the E-clock frequency is above 200 kHz (the E-clock frequency is one quarter the frequency of the on-board crystal). A reset is always triggered at E-clock frequencies below 10 kHz, and may be triggered at frequencies as high as 200 kHz.

The clock monitor is primarily used as a backup for the COP. The COP relies on the clock's presence for reliable operation, and the clock monitor can ensure that the processor is safely reset if the clock fails.

Enabling the clock monitor is accomplished by setting the CME (clock monitor enable) bit in the OPTION register. This bit may be set or reset at any time. A second bit named FCME (force clock monitor enable) is also involved. When the FCME bit is in its default state of 0, the bit has no effect, and when FCME is set, the clock monitor feature cannot be disabled until a reset occurs. We will assume that FCME is 0, and that the CME bit controls the clock monitor. See F1 p.6-5 for further details. Note also that if the clock monitor is enabled, a STOP assembly instruction will trigger a reset because it stops the clock, as discussed in the "Low Power Modes" section below.

The following simple words enable and disable the clock monitor:

HEX
8    CONSTANT    CME.MASK    \ define a mask for the enable bit in OPTION
8039  REGISTER:    OPTION    \ the OPTION register contains the CME bit
 
 
: CLOCK.MONITOR.ENABLE ( -- )
    CME.MASK OPTION SET.BITS
;
 
: CLOCK.MONITOR.DISABLE ( -- )
    CME.MASK OPTION CLEAR.BITS
;

The 68HC11F1 has two low power modes. These modes are enabled by assembly instructions STOP and WAI (wait). The STOP command puts the CPU into its lowest power-consumption mode by stopping all clocks, thereby stopping all processing (F1 p.6-17). If the clock monitor is enabled, a reset will be triggered when the clocks stop due to a STOP instruction. To use a STOP instruction when the clock monitor reset is enabled, disable the monitor before the STOP instruction, and re-enable it after returning from the STOP.

Pulling either /RESET, /IRQ or /XIRQ low wakes the processor up after a STOP instruction. Pulling the reset line low awakens the CPU and performs the standard reset startup sequence. Pulling /XIRQ low to awaken the CPU triggers a normal /XIRQ interrupt if the X bit in the CCR register is clear (i.e., if /XIRQ interrupts are enabled). After execution of the /XIRQ interrupt handler, processing returns to the instruction following the STOP command. If the X bit is set, (i.e., if /XIRQ is not enabled), pulling /XIRQ low awakens the CPU, but processing will begin at the instruction following the STOP instruction, and no interrupt will be called. For the CPU to be awakened by the /IRQ line going low, the I bit in the CCR register must be clear so that interrupts are globally enabled. When /IRQ goes low and the I bit is clear, execution begins with the /IRQ handler and then executes the code following the STOP instruction.

The STOP instruction is executed as a NOP unless the S bit in the CCR is cleared. After clearing the S bit, any occurrence of a STOP instruction puts the CPU into its lowest power mode. After each reset or restart, QED-Forth leaves the S bit in the CCR in its default set position, meaning that the STOP mode is disabled.

The following routines illustrate how to enable and disable the STOP instruction via the S bit. They also provide a general purpose word that can be called to enter the low power mode. This code relies on some definitions that were presented in the previous section.

CODE ENABLE.STOP    ( -- )
            TPA            \ get CCR contents into accumulator A
    7F    IMM    ANDA        \ clear the S bit, bit 7 of the CCR
            TAP            \ store to CCR, enabling STOP
            RTS            \ return
END.CODE
 
CODE DISABLE.STOP    ( -- )
            TPA            \ get CCR contents into accumulator A
    80    IMM    ORAA        \ set the S bit, bit 7 of the CCR
            TAP            \ store to CCR, so execution of STOP = NOP
            RTS            \ return
END.CODE
 
: ENTER.STOP.MODE ( -- )
    \ when executed, places the processor in the low power STOP mode,
    \ disabling the clock monitor first if it was enabled.
    \ When the processor re-awakens, it executes the final part of this
    \ word which re-enables the clock monitor if it had been enabled
    \ before the STOP mode was entered.
    OPTION C@ CME.MASK AND BOOLEAN    \ flag tells if clock monitor is enabled
    LOCALS{ &cmr.enabled? }
    &cmr.enabled?                \ If clock monitor is enabled,
    IF    CMR.DISABLE        \ then disable it before STOP
    ENDIF
    >ASSM
        STOP                \ enter stop mode until awakened...
    >FORTH                \ ...now that the CPU has been awakened...
    &cmr.enabled?                \ If the clock monitor reset was enabled before,
    IF    CMR.ENABLE        \ ...then re-enable it
    ENDIF
;

The WAI instruction also puts the 68HC11F1 in a low power mode. However, clocks are not disabled in the wait mode, so power consumption is greater than the STOP mode. After a WAI instruction, the machine state is stacked and processing stops. Power savings can be increased by setting the I bit in the CCR and disabling the COP. Further savings can be achieved by disabling the on-chip subsystems, including executing A/D8.OFF to turn off the A/D (F1 pp.6-17... 6-18).

The WAI low power state can only be exited by an unmasked interrupt or by pulling the /RESET pin low. When an unmasked interrupt occurs, (for example /IRQ or /XIRQ goes low, the COP is not serviced, clock monitor failure or reset occurs), the appropriate interrupt handler is executed and then processing continues with the instructions following the WAI. Implementing the WAI lower power mode is accomplished by simply executing WAI. For example:

CODE ENTER.WAI.MODE    ( -- )
        WAI        \ execute WAI
        RTS        \ return
END.CODE

In sum, power can be saved by putting the CPU in a low power mode while processing is not required. The 68HC11F1 has two low power modes with different degrees of savings. Both modes are terminated by unmasked interrupts. While the WAI instruction can be called without any preparation, the STOP instruction must be enabled by clearing the S bit of the CCR register.

One final signal produced by the 68HC11F1, but not easily classified, is named 4xOut (F1 p.2-4). This pin is accessible at pin 22 on the Digital I/O and Control bus. It is a buffered signal running at the same frequency as the on-board crystal. It can be used to drive the clock of another processor such as a second, synchronized 68HC11F1. F1 page 2-5 shows a circuit diagram which can be used for this purpose. On the QED Board the 4xOut signal is always enabled.

The 68HC11F1 microcontroller has four operating modes: expanded nonmultiplexed, special test, single chip, and special bootstrap modes (HC11 chapter 3 and F1 pp.2-1...3). The standard operating mode is expanded nonmultiplexed, meaning that the processor has access to expanded memory beyond its on-chip memory, and that the address and data lines are not multiplexed together (as they are on other members of the 68HC11 family). The QED Board also makes use of the special test mode, renaming it the "special cleanup" mode. This mode makes it possible to rapidly recover from any programming error that causes repeated machine crashes. The single chip mode takes away the ability of the processor to address external memory, and special bootstrap allows startup code to be inserted into the processor; these two modes are not used on the QED Board.

The processor's operating mode is determined by the states of two pins named MODA and MODB (refer to the schematic in Appendix A). On the QED Board, MODA is always high and MODB may be pulled LOW by turning onboard DIP switch #5 ON; this invokes the special cleanup mode. When DIP switch #5 is in its standard OFF position, the board is in the standard operating mode.

The Special Cleanup Mode is useful if a buggy startup routine has been installed (using the AUTOSTART or PRIORITY.AUTOSTART words) or if invalid register initializations have been specified (for example, using the INSTALL.REGISTER.INITS word). To recover from these problems, simply enter the special cleanup mode by keeping turning DIP switch #5 ON, and then powering up the board or pushing the reset button. This completely re-initializes the system software to its "pristine" state, and displays the QED Forth startup message at your terminal. To resume normal operation, return DIP switch #5 to the OFF position and execute another reset. The special cleanup mode is also discussed in the "Interrupts and Register Initializations" chapter in the QED Software Manual.

This chapter describes a variety of useful hardware features of the 68HC11F1. The processor's two external hardware interrupts, /XIRQ and /IRQ, may be used by external devices to request immediate service. Three nonmaskable interrupts cause a hardware reset: the external reset, the COP, and the clock monitor. The main reset is activated on power-up or when the /RESET pin is pulled low for more than 4 machine cycles. Enabling the computer operating properly circuit, COP, sets up a watchdog timer that resets the processor unless a special register is periodically updated. This provides a means of recovering from crashes in an embedded application. Use of the COP feature requires installation of an autostart routine which services the COP. The clock monitor backs up the COP by resetting the machine if the system clock fails. STOP and WAI instructions are available to put the CPU in low power modes with different degrees of power savings. A buffered clock signal, 4xOut, can be used to synchronize additional devices with the QED Board's processor. Finally, an on-board DIP switch allows selection of the standard operating mode or the special cleanup mode.