Table of ContentsConnecting to the 24/7 Data Acquisition Module Converter Noise and Effective Resolution Other Sources of Noise and Offset Error Tips For Measuring Small Voltages Addressing the 24/7 WildCard Using Module Select Jumpers Initializing the 24/7 Data Acquisition Wildcard Specifying the Reference Voltage Calibration Options Single- and Multi-Channel Sampling Continuous Sampling from a Single Channel |
24/7 Data Acquisition Wildcard Users GuideGlossaryFORTH: AD24_Multiple ( u/xaddr – [TRUE] or [TIMEOUT_ERROR] | u = num samples, xaddr = start_xaddr ) Acquires u samples from the 24 bit analog to digital (A/D) converter and stores the samples as sequential 32 bit values starting at the specified xaddr within a timeout period or a timeout flag is returned. The returned flag is either TRUE (0xFFFF) or the timeout flag (0x0009). Calls Pause while waiting for the samples. The timeout period is calculated using the following equation: Init_AD24, Use_Onboard_Ref or Use_External_Ref, and Start_Conversion or Start_Conv_With_Values must be called prior to this routine to initialize, configure, and calibrate the 24/7 Data Acquisition Wildcard. The maximum number of samples is limited to 8192 because this routine can only store data on a single page. The number of samples is clamped so the routine does not store results past a page boundary. No error flag is returned if an invalid number of samples is specified. This routine uses an interrupt service routine (ISR) tied to output compare 1 (OC1) to obtain samples from the A/D. The ISR runs at more than twice the frequency specified to Start_Conversion or Start_Conv_With_Values. This is done to eliminate clock variations between the A/D and QED clocks and to guarantee that a sample is not missed even if the ISR is delayed up to 1/2 a sample period or one full ISR period. The following equation is used to calculate the sampling period, the maximum acceptable delay time of the ISR, and the maximum time a routine or task can use the SPI: The INTERRUPT_LATENCY_DELAY is composed of 200 μs for the time to update the A/D data register with sample values, 10 μs of interrupt latency delay, and 50 μs to read the data ready line when the ISR is entered. The INTERRUPT_LATENCY_DELAY is a constant specified in ticks of TCNTs; ie. usually 2 microsecond counts. The processor’s TMSK2 register is read to determine the TCNT period. Do not change the resolution of TCNT during the execution of this routine. This routine is not re-entrant. If using in a multitasking system, be sure only one task calls this routine or be sure that separate tasks do not use the AD7714 at the same time. AD24_Multiple takes 1.60 ms to setup the ISR and do the error checking on the number of samples before checking the data ready line. |
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