Forth V4.0/V4.2 Functions that Disable Interrupts
Certain QED-Forth library routines in the V4 kernel temporarily disable interrupts by setting the I bit in the condition code register. These routines are summarized here to assist you in planning the time-critical aspects of your application.
The kernel provides a set of uninterruptable memory operators that disable interrupts for a few microseconds during the memory access. These are very useful in applications where several tasks or interrupt routines must access a shared memory location. The glossary entries for these words detail the length of time that interrupts are disabled.
| (CHANGE.BITS) | (CLEAR.BITS) | (SET.BITS) | (TOGGLE.BITS) | CHANGE.BITS |
| CLEAR.BITS | PIA.CHANGE.BITS | PIA.CLEAR.BITS | PIA.SET.BITS | PIA.TOGGLE.BITS |
| SET.BITS | TOGGLE.BITS | |2!| | |2@| | |F!| |
| |F@| | |X!| | |X@| |
Accessing the PIA (Peripheral Interface Adapter) and LCD display require the insertion of wait states, and the architecture of the QED Board requires that interrupts be disabled while a wait state memory access is in progress. In addition to the PIA routines listed above, the following routines disable interrupts to insert wait states:
| $>DISPLAY | (UPDATE.DISPLAY) | ?KEYPAD | ?KEYPRESS | CHAR>DISPLAY |
| CLEAR.DISPLAY | COMMAND>DISPLAY | DISPLAY.OPTIONS | INIT.DISPLAY | INIT.PIA |
| IS.DISPLAY.ADDRESS | KEYPAD | PIA.C@ | PIA.C! | PUT.CURSOR |
| UPDATE.DISPLAY | UPDATE.DISPLAY.LINE |
The multitasker mediates access to shared resources and ensures smooth transfer of information among tasks. The routines that manage resource variables and mailboxes must disable interrupts for short periods of time to ensure proper access to shared resources and messages. Consequently, the following routines temporarily disable interrupts:
| ?GET | ?RECEIVE | ?SEND | GET | RECEIVE | RELEASE | SEND |
Consult their glossary entries for details.
The following routines temporarily disable interrupts to ensure that a new task is not corrupted while it is being built:
| BUILD.STANDARD.TASK | BUILD.TASK |
These routines disable interrupts to ensure that the elapsed time clock is not updated while it is being read:
| READ.ELAPSED.SECONDS | READ.ELAPSED.TIME |
The multitasker is charged with smoothly transferring control among tasks via timeslicing or cooperative task switching. The timeslicer is an interrupt service routine associated with output compare#2. It disables interrupts for the duration of a task switch which requires 25 microseconds plus 3.25 microseconds for each ASLEEP task encountered. The cooperative task switch routine
PAUSE
switches tasks in (27 + 3.25n) microseconds, where n is the number of ASLEEP tasks encountered in the round robin task list. Of this time, interrupts are disabled for (20 + 3.25n) microseconds.
The PAUSE routine (which temporarily disables interrupts) is called by the following built-in device drivers:
| EMIT | EMIT1 | EMIT2 | KEY | KEY1 | KEY2 | ?KEYPAD | KEYPAD |
The following device driver routines GET and RELEASE resource variables, and so disable interrupts for short periods of time:
| ?KEY | ?KEY1 | ?KEY2 | ?KEYPAD | ?KEYPRESS |
| A/D12.MULTIPLE | A/D12.SAMPLE | A/D8.MULTIPLE | A/D8.SAMPLE | PAUSE.ON.KEY |
| >DAC |
The battery-backed real-time clock option shares the RAM socket on the QED Board. While the "watch" is being read or set by the routines
READ.WATCH SET.WATCH
the RAM cannot be accessed, so interrupts cannot be properly serviced. Therefore these routines disable interrupts for approximately 0.5 msec while the watch is being accessed.
All of the routines that write to the EEPROM disable interrupts for 20 msec per programmed byte. This results from the 68HC11's design which prohibits any EEPROM locations from being read while other EEPROM locations are being modified. Since all interrupts are vectored through EEPROM, interrupts cannot be serviced while an EEPROM storage operation is in progress. The following fundamental EEPROM storage routines
| (EEC!) | (EE!) | (EEX!) | (EEF!) | (EE2!) |
disable interrupts for 20 msec per programmed byte. These routines are smart enough to avoid programming a byte that already has the correct contents. The following routines may modify EEPROM locations:
| ATTACH | AUTOSTART | COLD.ON.RESET | DEFAULT.REGISTER.INITS |
| DOWNLOAD.MAP | INIT.VITAL.IRQS.ON.COLD | INSTALL.MULTITASKER | INSTALL.REGISTER.INITS |
| IS.DISPLAY | NO.AUTOSTART | SAVE | SERIAL1.AT.STARTUP |
| SERIAL2.AT.STARTUP | STANDARD.MAP | STANDARD.RESET | START.TIMESLICER |
All of the routines that write to the Flash memory disable interrupts for 20 msec per programmed sector, where a standard sector is 256 bytes. This results from the flash architecture which prohibits any flash locations from being read while other flash locations are being modified. Since interrupts invoke flash-resident code, interrupts cannot be serviced while an flash storage operation is in progress. The following flash routines disable interrupts:
| PAGE.TO.FLASH | PAGE.TO.RAM | PRIORITY.AUTOSTART | TO.FLASH |
The following routines disable interrupts and do not re-enable them:
| DISABLE.INTERRUPTS | SEI | COLD | WARM |
DISABLE.INTERRUPTS and its assembly language counterpart SEI explicitly set the I bit in the condition code register. The routines ENABLE.INTERRUPTS and CLI clear the I bit to globally enable interrupts. The restart routines COLD and WARM disable interrupts so that the initialization process is not interrupted.
Note: Software development in Forth uses the Mosaic IDE Integrated Development Environment; this is the same IDE used for software development in C. While Forth programmers will not use the IDE's C compiler, the IDE provides a full-featured text editor and customized terminal for rapid Forth code downloads and interactive Forth debugging sessions with the 68HC11 processor on the controller board.